28% Area Reduction on an Encryption Module — Without Touching Timing

Our customer is a semiconductor company building security-sensitive products across industrial, automotive, and consumer electronics markets. Their SoC designs embed encryption modules at multiple points in the chip — protecting data pipelines and securing communication interfaces that their end customers depend on.

They came to FiLabs with a mature, proven design — not a prototype. The encryption module had already taped out and was in active production. What they wanted was straightforward to state but hard to deliver: reduce the area footprint meaningfully, without touching timing, and without a weeks-long re-spin cycle.

With a growing queue of derivative SKUs and customer-specific variants, every week spent re-iterating a single module was a week their roadmap  move. Speed and accuracy weren't nice-to-haves. They were the constraint.

Same Spec. Tighter Silicon.

“The traditional path — rewrite RTL, tune synthesis, run ECO iterations — takes 4 to 5 weeks. And there's no guarantee you've found the global optimum.”

Manual RTL optimization is inherently constrained by how many variants an engineer can reasonably explore in a given time window. Synthesis iteration averages 3–5 rounds, each taking 1–2 weeks. Most of that time is spent waiting — not deciding.

A Coordinated Agent Pipeline — Not a Tool

FiLabs deployed its Spec-to-RTL Agent system, running the full flow from specification parsing to verified, synthesis-ready RTL delivery. Each agent owns a distinct stage and shares a persistent representation of intent, constrign state.

Intent-Level Parsing. Thousands of Variants. Zero Regression.

The Numbers

28% area reduction. Zero timing compromise. Delivery in 0.1 days — down from 4–5 weeks. Functional equivalence formally verified.

28% area is not a small number.

At 22nm and 28nm — the dominant nodes for industrial, automotive, and consumer electronics — area maps directly to per-die cost. This module is typically instantiated multiple times across an SoC, meaning the area savings compound across the full chip. At production volumes, this translates into millions of dollars in cumulative cost reduction.

Smaller area also means lower dynamic power, which is particularly valuable in power-constrained product categories.

Why is traditional design so slow here?

RTL optimization is a high-dimensional search problem. Engineers navigate it with experience and heuristics — not exhaustive experation is slow, and most of a project's calendar time is consumed by waiting cycles between tool runs, not actual decision-making.

FiLabs runs thousands of design variants in a single pass, compressing what used to be weeks of back-and-forth into a fraction of a working day. The bottleneck shifts from iteration speed to engineer review — which is exactly where expert judgment belongs.